In integrated circuits, there is generally a piece of silicon known as a die or chip which contains electrical circuits and which is connected to a lead frame. The chip has bonding pads which are connected to the lead frame by tiny wires. The lead frame has leads which are used for connecting to a printed circuit board as part of a larger system. The leads of the lead frame have a certain amount of inductance as well as capacitance and resistance. There is also some inductance in the wire from the bonding pad to the lead frame. This wire inductance, however, is significantly less than that of the lead frame. The connection of a lead of the lead frame to a circuit board also adds some inductance. As the switching speeds of integrated circuits have increased, this cumulative inductance has begun to have an impact on the performance of the integrated circuit.
Of course it is desirable to have integrated circuits which are very fast. The increased switching speed has also increased the rate at which current changes. This increased rate of current change causes a voltage drop across the inductance. The voltage across an inductance is equal to the inductance times the time rate of change of the current through that inductance. This is expressed as Ldi/dt, where L is the inductance and di/dt is the time rate of change of the current. As the di/dt becomes larger, the voltage across the inductance becomes larger. This voltage drop across an inductance causes a voltage differential between the lead location on the circuit board and the bonding pad to which it is connected on the integrated circuit. This can create a problem of having the internal supply at different voltage than the voltage of the external supply.
This problem can be described by reference to FIG. 1 which shows a portion of an integrated circuit comprised of an output buffer 11, an internal positive power supply terminal VCCin connected to an external positive power supply terminal VCCex, an internal negative power supply terminal VSSin connected to an external negative power supply terminal VSSex, an internal output terminal Qin connected to an external output terminal Qex. Output buffer 11 receives power from its connections to VCCin and VSSin. In typical currently used integrated circuits, VCC is nominally 5 volts. Output buffer 11 provides an output on Qin. VCCin is an internal bonding pad on the chip portion of the integrated circuit. VCCex is the tip of one of the leads of the lead frame portion of integrated circuit 10. VSSin is an internal bonding pad on the chip portion of integrated circuit 10. VSSex is the tip of one of the leads of the lead frame portion of integrated circuit 10. Qin is an internal bonding pad on the chip portion of integrated circuit 10. Qex is the tip of one of the leads of the lead frame portion of integrated circuit 10. Inductances indicated as L1, L2, and L3 represent the inductances present by virtue of the connections between VCCin and VCCex, VSSin and VSSex, and Qin and Qex, respectively.
When output buffer 11 switches logic states, there will be a change in the current flowing into or out of output buffer 11 with respect to Qin. The amount of the current flowing will depend at least somewhat on a load which will be present on Qex. If the current changes so that more current is flowing to Qin, there will also be more current flowing from VCCin to output buffer 11 which in turn means that more current will be flowing between VCCex and VCCin. This change in current flow will cause a voltage drop between VCCin and VCCex by virtue of inductance L1. This voltage drop will be proportional to how rapidly the current changes between VCCin and VCCex. The expression for this voltage drop is L1di/dt. The L1di/dt voltage drop is thus the difference between the power supply voltage which is present on the circuit board and the internal power supply which is used to drive the internal circuitry of integrated circuit 10. If this L1di/dt becomes sufficiently large, the logic state of other inputs to integrated circuit 10 can be misinterpreted. What the external circuit board interprets as a logic low may be interpreted as a logic high by integrated circuit 10 because the internal power supply voltage is so low. Although this differential between internal and external power supply voltage is only for the duration of the high rate of change of current, this can result in providing an erroneous output in an integrated circuit that is externally clocked or a significant delay in providing a valid output in an integrated circuit that is static.
The same type of situation can occur for the case in which output buffer 11 begins sinking current from Qin. In such case there will be a current change between output buffer 11 and VSSin which will also be present between VSSin and VSSex. The consequent change in current flow through L3 will cause a voltage drop between the internal VSSin and the external VSSex. This will have the effect of raising the voltage of the internal ground (VSS) above that of the circuit board ground. If this voltage differential becomes sufficiently large, then inputs to integrated circuit 10 may be misinterpreted. A signal which is a logic high with respect to the circuit board which is using VSSex as the ground reference, may be interpreted by integrated circuit 10 as a logic low because VSSex is too high of a voltage. This is in fact in general the more severe problem because in general a logic high is guaranteed as being recognized as a logic high when it is below one half of the power supply voltage. For example, in a typical 5-volt power supply MOS circuit, it is guaranteed that a signal will be recognized as a logic high even if it is only 2.0 volts. Such an input will then be more susceptible to making a false detection when there are fluctuations in an internal ground than when there are fluctuations in the internal 5-volt power supply terminal.
One conventional solution has been to keep the device sizes of the output buffer sufficiently low so that the output buffer does not cause too large of a current change. This of course is a sacrifice of speed. Another solution has been to add more power supply leads so that the current change is spread over more leads. More leads can be viewed as placing inductors in parallel which decreases the inductance. This adds to the cost of the package as well as requiring more space on the circuit board which uses the particular integrated circuit. Another approach has been to precharge the output to a logic low prior to valid data appearing on the output. This takes advantage of the more severe problem that occurs during a logic high to logic low transition. It is, however, generally desirable for the output to be high impedance (commonly known as tri-stated) when it is not valid. An example of this approach is shown in U.S. Pat. No. 4,661,928, Yasuoka.
The typical di/dt response to a typical logic state transition of a MOS type output is shown in FIG. 2. Shown in FIG. 2 is the logic low to logic high case. The transition begins at tim t0 and is complete at a time t1. The resulting change in current is shown as di/dt. A positive spike begins at time t0 when the current is increasing most rapidly. The rate of change of current falls off rapidly and becomes negative. The current is stabilized at time t1. The maximum height of the di/dt spike causes the maximum voltage differential between the internal power supply and the external power supply. Another solution is to provide a second pull-down device in the output buffer which is driven from an RC delayed signal so that there is somewhat of a stagger effect in changing the current flow. This results in two di/dt spikes so that the maximum spike height is lowered. This is an improvement but still not optimum. The problem has been most frequently seen in output buffers but internal buffers can have the same problem if there is a large current change. One example is the simultaneous precharging of the bit lines of a memory.
Shown in FIG. 3 is a desired shape of the time rate of change of the current drawn by a buffer, particularly for buffers which cause a large current change, such as an output buffer or a driver for precharging bit lines. To achieve a logic state change, there is some amount of charge which must be transferred. There is a steady state charge flow, or current, which must be sustained after the logic state has been changed. There is also capacitance which must be charged as part of the logic state change. Assuming that a logic state change is to be completed within the time from t0 to t1, the optimum di/dt curve is shown in FIG. 3. The rate of current change will be zero until time t0. At time t0, di/dt will reach a certain value and remain at that level until about half way through the logic state change. At that point the current needs to decrease to the steady state condition. This decrease should also occur at a constant rate until time t1. Although the negative portion of di/dt can potentially be as significant of a problem as the positive side, this is not generally the case. The nature of the circuitry generally causes slow changes as the steady state condition is approached. The nature of MOS transistors is such that when they are in the triode region, the current is proportional to the drain to source voltage. As the transistor that is charging an output node has its drain and source connected between a power supply terminal and the output node so that as the node becomes charged, the drain to source voltage decreases so that the current is reduced. There is thus in the nature of output transistors a relatively smooth di/dt reduction. Also the new logic state is actually reached before the steady state condition is reached. For example, a buffer ay provide a logic high at a steady state of 5 volts but a logic high is certain to be recognized when 4 volts is reached. In such case the rate at which the output moves from 4 volts to 5 volts is not significant. Consequently, the di/dt reduction is not generally a major consideration. The objective then is to reach the level at which a logic high is certain to be detected as fast as possible without causing a di/dt which is too great. A constant di/dt is thus the goal for at least the first half of the logic state transition. Improvements over the performance shown in FIG. 2 was disclosed in U.S. patent application Ser. No. 911,702, Dehganpour et al, filed Sept. 26, 1986, and U.S. patent application Ser. No. 081,194, Yu et al, filed Aug. 4, 1987, both assigned to the assignee hereof. The present invention is believed to offer advantages over the inventions disclosed in those applications.